1. Technical Field of the Invention
The present invention relates to a process for forming bumps on electrodes formed on a substrate. In particular, the present invention relates to a process for forming fine bumps having improved uniformity on electrodes arranged at a fine pitch.
2. Description of the Related Art
With the development of high density and high integration of a semiconductor integrated circuit (LSI) used for electronics device, higher pin count and finer pitch of electrode terminals of a LSI chip have been rapidly developed in recent years. The LSI chip is mounted over a wiring substrate by generally employing a flip chip mounting process in order to decrease wiring delay. It is common practice in this flip chip mounting process to form solder bumps on the electrode terminals of the LSI chip, and then connect, through such solder bumps, all the electrode terminals to all electrodes formed on the wiring substrate in a batch process.
For mounting a next-generation LSI having 5000 or more electrode terminals over the wiring substrate, it is necessary to form fine-pitch bumps with a pitch of 100 μm or less. It is, however, difficult for a conventional solder bump forming process to form such fine-pitch bumps. Moreover, from a viewpoint that a large number of bumps must be formed according to the number of the electrode terminals, high productivity is required to reduce manufacturing cost by reducing mounting tact time per chip.
There has been conventionally developed a plating process and a screen printing process as a bump forming process. The plating process is convenient for achieving the fine pitch, but it is complicated and compromises the productivity. The screen printing process, on the other hand, has high productivity, but is not convenient for achieving the fine pitch because a mask is used.
Recently, there has been developed several processes for selectively forming solder bumps on electrodes of a LSI chip or wiring substrate. These processes are not only convenient for forming fine bumps, but also convenient for achieving a high productivity since a plurality of the fine bumps can be formed in a batch process. Accordingly they are promising processes that can be applicable to the mounting of the next-generation LSI over the wiring substrate.
According to one of these promising processes, a solder paste comprising a mixture of solder powder and a flux is applied directly onto a substrate having electrodes thereon, and subsequently the substrate is heated so as to melt the solder powder and then form the bumps selectively on the electrodes having high wettability without causing an electrical short circuit between the adjacent electrodes. See Japanese Patent Kokai Publication No. 2000-94179 (which is hereinafter referred to also as “Patent literature 1”), for example.
There is also another process wherein a paste composition (so-called “deposition type solder using chemical reaction”) mainly comprising organic acid lead salt and tin metal is applied directly onto a substrate, and subsequently the substrate is heated so as to induce a displacement reaction for Pb and Sn, and thereby Pb/Sn alloy is selectively deposited on electrodes of the substrate. See Japanese Patent Kokai Publication No. H01-157796 (which is hereinafter referred to also as “Patent literature 2”) and “Electronics Packaging Technology”, issued on September 2000, pp. 38-45 (which is hereinafter referred to also as “Non-patent literature 1”), for example.
There is also another process which selectively forms molten solder on electrodes, by immersing a substrate having electrodes thereof in a chemical solution so as to form an adhesive film only on surfaces of the electrodes, and then putting solder powder into contact with the adhesive film so as to attach the solder powder to the electrodes and subsequently heating the substrate. See Japanese Patent Kokai Publication No. H07-74459 (which is hereinafter referred to also as “Patent literature 3”) and “Technical Report of IEICE, EMD96-15” (which is hereinafter referred to also as “Non-patent literature 2”), for example.
In the meantime, Japanese Patent Kokai Publication No. 2001-219294 (which is hereinafter referred to also as “Patent literature 4”) discloses a solder paste which is formed by kneading solder powder and a resin having a flux. Moreover, there is a proposed process for mounting a semiconductor chip over a substrate by using a resin comprising a low-melting-point metal filler. See Japanese Patent Kokai Publication No. 2004-260131 (which is hereinafter referred to also as “Patent literature 5”), “10th Symposium on “Microjoining and Assembly Technology in Electronics” Feb. 5-6, 2004, pp. 183-188 (which is hereinafter referred to also as “Non-patent literature 3”) and “9th Symposium on “Microjoining and Assembly Technology in Electronics” Feb. 6-7, 2003, pp. 115-120 (which is hereinafter referred to also as “Non-patent literature 4”). In this proposed process, self-aligned formation of metal connection is performed between the substrate and the semiconductor chip by melting the metal filler (i.e., electrically conductive particles) contained in the resin. However, there is nothing else that primarily studies the mechanism of the self-aligned formation of the metal connection is, especially in Non-patent literature 3 and Non-patent literature 4.
It is also disclosed to use a reducing resin in Non-Patent literature 3, Non-Patent literature 4 and Patent literature 5 cited above. This reducing resin is a so-called “no-flow type underfill material” (see Japanese Patent Kokai Publication No. 2001-329048 for example). When acid anhydride serving as a curing agent is added to the reducing resin, the acid anhydride is hydrolyzed to produce carboxylic acid, and thereby a flux property is obtained.